Semiconductor devices are manufactured by forming active regions in a semiconductor substrate, depositing various insulating, conductive, and semiconductive layers over the substrate, and patterning them in sequential steps. The upper or last-formed layers of the semiconductor device typically comprise metallization layers. The metallization layers typically comprise one or more layers of metal interconnect having conductive lines disposed within an insulating material and may provide connections to underlying active regions and connections within and over the substrate. Integrated circuit chips may be attached to a lead frame and then packaged in a ceramic or plastic carrier.
As the cost of shrinking semiconductor devices continues to increase, however, alternative approaches, such as extending the integration of circuits into the third dimension or semiconductor substrate stacking are being explored. Two or more substrates are bonded together to form a three-dimensional structure.
In a known manufacturing process, a contact pad metal layer is deposited and patterned over the substrate. A passivation dielectric layer is formed on the contact pad metal layer. Openings are formed in the dielectric layer to expose the contact pads. As a result, the contact pads are recessed into the chip's surface. To connect the contact pads to the printed circuit board (PCB), protruding metal bumps are formed on the contact pads. Bumps are bonded to PCB contact pads with solder, an adhesive, or by thermal or thermosonic compression.
Bumps may be made of solder. The die is placed on the PCB with bumps on metal pads and solder is reflowed to form solder joints. Thus, the attachment may be mechanically strong and reliable in the presence of thermal stresses, but the solder bumps are difficult to scale down as contact pads become smaller and the pitch between the pads is reduced. As the solder bump sizes decrease to accommodate the smaller contact pads and pitches, the solder joints become mechanically and thermally weaker. In addition, the solder ball (solder bump) size defines the standoff distance between the chips. If the standoff is too small, there will be increased fatigue stresses on the solder joints during thermal cycling.
Moreover, in solder bump interconnects, solder wetting onto bond pads is a key factor that determines the interconnect process yield and the solder joint reliability. Solder wetting involves various physical attributes such as surface tension imbalance, viscous dissipation, molecular kinetic motion, chemical reaction, and diffusion. The degree of wetting may be described by the contact angle, the angle at which the liquid interface meets the solid interface. The degree of wetting between the copper and conventional eutectic solder may not be optimum. If the wetting is poor, the solder may form a compact droplet on the copper surface, leaving insufficient area bonded between the copper and the eutectic solder.
Further, solder joint reliability may be a problem in that copper easily oxidizes and may oxidize during the solder process. If the copper oxidizes, a good electrical contact may not be provided. Moreover, the relatively large size of the solder bumps, which may be in the range of tens of microns and greater, is not conducive to shrinking devices.